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More useful work per evaluation — with lower switching power, fewer reduction stages, and improved sustained throughput.
DRDCL: A New CMOS-Compatible Logic Structure
DRDCL, Dynamically Reconfigurable Differential Cascode Logic, is a CMOS-compatible digital logic structure designed to increase useful computation per transistor, per cycle, per mm² and per joule. DRDCL combines differential cascode trees with dynamic Cross-Switch output control. One evaluated structure can support multiple related functions, produce multiple useful outputs and rapidly reconfigure for different required operations. SoftChip packages these structures as bounded, characterizable logic blocks for integration into conventional semiconductor design flows. Soft-NMC, near-memory reduction for AI inference, is the first commercial application.
Conventional Logic vs DRDCL
Conventional gate-based CMOS often implements related score, select, mask, and control functions as separate logic paths.
As functions become more complex, this increases:
- logic duplication
- switching activity
- routing complexity
- intermediate movement
- local staging depth
DRDCL takes a different approach.
One evaluated tree can support multiple related functions and produce multiple useful outputs per evaluation.
The result is not simply smaller logic.
It is more useful work per evaluation.
Conventional CMOS
- Separate fixed networks for each function and output
- More transistors and local stages
- More intermediate switching and routing
- Repeated evaluation of common inputs
- Additional movement between logic stages
DRDCL
- Common evaluation of related functions
- Multiple useful outputs from one evaluated structure
- Rapid function changes within the same structure
- Fewer stages and intermediate transitions
- More useful computation per cycle, area and joule
Dynamically Reconfigurable Differential Cascode Logic
The combination of common evaluation, multiple useful outputs, lower intermediate switching and nanosecond-scale reconfiguration allows DRDCL to perform more required work within a smaller logic and energy budget.
- multiple functions per evaluation
- multiple useful outputs
- nanosecond-scale reconfiguration
- lower intermediate switching
- fewer local logic stages
- improved computation per transistor, cycle, mm² and joule
- bounded timing, power, area and PVT characterization
Characterizable
Logic IP
SoftChip’s initial deliverables are bounded DRDCL logic blocks designed to be evaluated, characterized, benchmarked and integrated into existing semiconductor design flows.
Best-Fit Workloads
DRDCL is particularly valuable where related functions, repeated evaluations, multiple required outputs or excessive staging create a high transistor, switching, latency or area cost.
- streaming reduction
- scoring, selection and accumulation
- arithmetic and output-control logic
- memory-adjacent compute
- multi-output related functions
- control, scheduling and dataflow logic
- networking and signal processing
- sensor fusion and ADAS
- repair, remapping and resilient spare logic
- adaptive compute structures
These functions appear across AI inference, memory-interface logic, networking, DPUs, baseband processing, sensor fusion, ADAS, adaptive compute, and control/dataflow systems.
First Focus: Stream / Reduce / Accumulate
SoftChip’s first implementation focus is Stream / Reduce / Accumulate logic for workloads that repeatedly score, select, reduce, accumulate, gate or update local state as data moves through a system. This provides a bounded starting point for demonstrating DRDCL’s ability to perform more useful work per evaluation while reducing intermediate movement and staging.
Soft-NMC: Reduction Before Movement
AI inference is increasingly constrained by K/V traffic movement during decode, not peak compute.
As context windows grow, attention repeatedly revisits prior K/V entries through the memory interface and compute fabric.
Soft-NMC applies DRDCL near the memory interface to reduce K/V-derived traffic before it travels deeper into the accelerator.
Soft-NMC is designed to:
- reduce K/V-derived traffic
- perform local reduction closer to memory
- preserve standard attention semantics
- improve sustained decode throughput
- support per-channel deployment
Candidate functions include scoring, selection, reduction, accumulation, masking, gating, local maximum tracking, normalization assistance and controller-side dataflow logic.
Soft-NMC can be placed near the memory-channel interface without changing the DRAM cell or the mathematical result of attention.
Architecture-model targets
- 60–80% less K/V-derived movement
- 12–13x higher local throughput
- 3–4x potential sustained system throughput in memory-bound inference
- Under 1% targeted area overhead at the memory-channel boundary
Soft-NMC does not change what attention computes. It changes where selected reduction happens.
Quantified Technical Foundation
Historical differential cascode logic demonstrated approximately 2x higher speed and approximately half the dynamic power of conventional CMOS in prior comparisons. For suitable functions, producing five useful outputs from one evaluation, combined with the historical circuit-speed advantage, can provide approximately 10x effective local throughput.
Structural estimates for equivalent sets of related functions indicate substantially higher logic density as tree depth increases:
- Three-level structure: approximately 134x
- Four-level structure: approximately 1,200x
- Five-level structure: approximately 5,200x
In-Logic State Retention:
Results Held Inside the Logic
IN-LOGIC STATE RETENTION Selected DRDCL trees may retain intermediate results locally, potentially reducing the number of conventional latches required for short-lived state and helping make precharge transparent to surrounding computation.
DRDCL Platform Roadmap
Soft-NMC
Near-memory scoring, selection, reduction and accumulation for AI inference.
Stream / Reduce / Accumulate
Bounded logic blocks for reduction, arithmetic, gating, output control and local state updates.
Future DRDCL Applications
Memory-interface logic, networking, adaptive control, repair and remapping, signal processing and other high-value logic functions.
How Partners Evaluate DRDCL
SoftChip works with semiconductor, AI hardware, and foundry ecosystem partners to evaluate where DRDCL can outperform equivalent CMOS logic. Initial engagements focus on bounded DRDCL logic blocks with clear PPA targets, defined interfaces, integration assumptions, and measurable benchmark criteria. The goal is to evaluate DRDCL in a practical implementation context, without requiring a wholesale change to existing design flows.
Evaluate DRDCL against CMOS where the PPA penalty is measurable and the integration path is bounded.
Evaluation steps
- Identify a high-value reduction or control function
Target logic where repeated evaluation, intermediate movement, or duplicated CMOS structures create a measurable PPA penalty.
- Define the conventional CMOS baseline
Establish equivalent functionality, timing target, area, power, and integration assumptions.
- Map the function into a bounded DRDCL logic block
Implement the selected function as a characterizable, interface-defined block rather than a broad change to the design flow.
- Characterize timing, power, area, and PVT behavior
Measure the DRDCL implementation against the CMOS baseline across relevant operating conditions.
- Benchmark useful work per evaluation
Compare not only gate count or frequency, but the amount of useful computation completed per cycle, per mm², and per joule.
- Define the integration path
Package the result for customer evaluation, NRE expansion, function customization, or IP licensing.
Engagement models
- Targeted DRDCL logic-block evaluation
A focused comparison of one high-value function against a conventional CMOS implementation.
- NRE-funded logic-block development
A structured engagement to implement, characterize, and benchmark a DRDCL logic block for a customer-relevant use case.
- Customer-specific function mapping
Translation of selected reduction, control, arithmetic, or memory-adjacent functions into DRDCL structures.
- Soft-NMC / memory-interface evaluation
Assessment of DRDCL-based logic near the memory boundary to reduce movement before traffic crosses the fabric.
- Foundry- and flow-compatible characterization
Timing, power, area, and PVT characterization designed to support practical integration review.
- IP licensing and product integration
Commercial licensing of validated DRDCL logic blocks for customer-specific silicon programs.
Evaluate DRDCL Logic IP Against Your CMOS Baseline
SoftChip is working with semiconductor, AI hardware, memory and foundry ecosystem partners on bounded logic-block evaluations with defined technical benchmarks, integration assumptions and commercial milestones.