In practice, systems are typically constrained by one of two costly bottlenecks:
Timing waste — stalls, tail latency (p99), and determinism workarounds
Data-movement waste — bandwidth underutilization and rising cost per operation
Addressing the wrong bottleneck first rarely helps. We focus on recognizing and relieving whichever is dominant in a given design.
100 - 100,000x higher than traditional CMOS
"Less Silicon. More Intelligence."
10X+ improvement over conventional designs
"The Power Revolution in Silicon",
Dynamic adaptation during operation
"Hardware That Adapts Like Software"
12x+ throughput improvement
"Extending Moore's Law"
SoftChip is developing a reconfigurable logic fabric (DRDCL) to reduce dominant sources of waste in modern chiplet-based systems.
We explore two system-centered expressions of our logic fabric:
Soft-TTC: reduces stalls and tightens p99 by eliminating waiting on critical paths.
Soft-NMC: reduces data movement near memory to improve effective bandwidth and cost per operation.
Both are built on the same underlying DRDCL concept.
Early-stage development; engineering-driven with an emphasis on silicon-validated results rather than abstract benchmarks.
For inquiries about timing or memory-centric evaluations, pilot engagements, or partnership opportunities, please reach out via our Contact page.
SoftChip was founded by three experienced semiconductor industry veterans who previously worked together at Intel. Our combined expertise in chip design, architecture, and engineering has enabled us to create the revolutionary DRDCL technology. Our team is passionate about transforming semiconductor design with cutting-edge technology that delivers unmatched power efficiency, flexibility, and performance.
Join the future of chip design with SoftChip’s DRDCL technology. Whether you’re developing for consumer electronics, automotive, or AI-driven devices, our technology provides a flexible, efficient, and scalable solution. Contact us today to start the conversation.