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Technical Evaluation

From Differential Cascode Logic to DRDCL

SoftChip’s research builds on decades of differential cascode logic development, including foundational circuit work at IBM.  DRDCL extends that foundation with dynamic Cross-Switch output selection, allowing one evaluated tree to support multiple related functions, produce multiple useful outputs and rapidly change its required function.  Our research evaluates how DRDCL can increase useful computation per transistor, per cycle, per mm² and per joule across AI, memory-interface, arithmetic, control and adaptive-logic applications.

Technical Papers

Example comparison of DRDCL versus conventional gate-based logic.

Foundational paper supporting the patent applications.

SoftChip is extending this work into architecture-level evaluations for AI inference, memory-interface logic, and Stream / Reduce / Accumulate datapaths.

Current Research Focus

SoftChip is currently focused on DRDCL applications where local reduction can improve useful throughput and energy efficiency.

Key research areas:

  • Multi-output DRDCL evaluation

Producing multiple useful outputs from one evaluated structure.

  • Stream / Reduce / Accumulate logic

Local scoring, gating, accumulation, and output-control logic.

  • AI inference and memory-interface reduction

Reducing K/V-derived movement while preserving attention semantics.

  • In-logic state retention

Using selected charged logic structures for short-lived state.

  • Repair and remapping

Applying rapidly reconfigurable logic to resilient spare structures.

  • Characterizable logic IP
Packaging bounded logic blocks for timing, power, area and PVT evaluation.

Research Claims and Validation

SoftChip distinguishes between circuit-level DRDCL advantages, architecture-model estimates, and measured silicon results.

Current architecture modeling suggests that selected memory-bound inference datapaths may achieve:

  • 60–80% targeted reduction in K/V-derived data movement
  • 12–13x potential local throughput improvement
  • 3–4x potential sustained system throughput improvement
  • Under 1% targeted area overhead at the memory-channel boundary

These are architecture-model estimates, not measured silicon results. Actual results depend on model architecture, sequence length, batch size, precision, attention variant, memory bandwidth, and integration point.

Evaluate DRDCL Against a Conventional CMOS Baseline

SoftChip is looking for semiconductor, AI hardware, and foundry ecosystem partners to evaluate bounded DRDCL logic implementations against equivalent conventional CMOS designs.

More useful computation per transistor, per cycle, per mm² and per joule.

Start a Technical Evaluation

EMERGING DRDCL CAPABILITIES

Research directions that extend beyond current characterized logic IP products.

Latch-Boundary Criticism

Earlier differential cascode logic encountered questions regarding latch boundaries and precharge behavior.

Precharge Hiding

Selected DRDCL trees may help hide precharge activity while reducing dependence on separate storage for short-lived state.

Selected Trees Acting as Temporary Storage

Certain structures may retain intermediate results locally and act as distributed latch-like elements.

Why This Is Not SRAM/DRAM Replacement

These capabilities are intended for short-lived state and are not intended to replace conventional memory structures.

Why It Matters

Soft-NMC

Memory-adjacent reduction and local state.

Soft-TTC

Timing, control, and throughput fabrics.

ARMOR

Broader architectural opportunities.