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Technical Evaluation

DRDCL: A New Logic Structure for More Efficient AI Hardware

More useful work per evaluation — with less duplicated logic, lower switching power, and better sustained throughput.

SoftChip is developing DRDCL-based near-memory reduction technology for AI inference and other reduction-heavy workloads. Our first application, Soft-NMC, reduces K/V-derived traffic before it crosses the wider memory interface and compute fabric.

Rethinking
How Logic Is Built

Conventional digital logic decomposes computation across many gates and stages.

That increases:

  • transistor count
  • intermediate switching
  • routing complexity
  • latency
  • power dissipation
  • data movement

SoftChip takes a different approach.

 

DRDCL uses differential cascode tree structures with dynamic Cross-Switch output selection. One evaluated tree can support multiple related functions and produce multiple useful outputs per evaluation.

Instead of building separate fixed paths for every related score, select, mask, or control function, DRDCL does more useful work inside fewer evaluated structures.

Instead of hardwiring separate fixed CMOS networks for every function, DRDCL can reuse the same evaluated structure across related operations and, in some cases, produce multiple useful outputs from one evaluation.

The result is not just smaller logic.

 

It is more useful work per evaluation.

Multi-Output Evaluation Improves Useful Work per Watt

SoftChip’s advantage starts with shared evaluation.
DRDCL can reduce the number of logic stages and duplicated transistor structures required for complex or related operations.

  • higher effective throughput
  • fewer intermediate steps
  • reduced switching activity
  • lower dynamic power
  • smaller area for equivalent work

In DRDCL, density is not the starting assumption.
It is the result of doing more useful computation inside fewer structures.

DRDCL macro IP semiconductor architecture with integrated logic routing and silicon structures

Characterizable Logic IP First

SoftChip’s first commercial products are bounded DRDCL logic blocks designed to be evaluated, characterized, and integrated into existing semiconductor design flows.

These blocks include DRDCL differential cascode trees, Cross-Switch control, precharge/evaluate timing, conventional digital interfaces, and timing/power/area characterization.

This lets customers evaluate DRDCL in specific high-value functions before considering broader DRDCL-enabled architectures.

First Focus: Stream / Reduce / Accumulate

SoftChip’s first focus is Stream / Reduce / Accumulate logic for workloads that repeatedly score, reduce, accumulate, gate, or update local state as data moves through a system.

These paths appear in AI inference, memory-interface logic, networking, signal processing, sensor fusion, ADAS, and control/dataflow systems.

 

The goal is to reduce intermediate movement by performing useful local reduction as data streams through the block.

Soft-NMC: Reduction Before Movement

AI inference is increasingly constrained by K/V traffic movement, not peak compute. As context windows grow, attention repeatedly revisits prior K/V entries during decode.

Soft-NMC applies DRDCL near the memory interface to reduce K/V-derived traffic before it travels deeper into the accelerator.

  • reduce K/V-derived traffic at the source
  • perform local reduction closer to memory
  • preserve standard attention semantics
  • improve sustained tokens/sec
  • support per-channel deployment
  • reduce traffic, not eliminate all K/V reads

Soft-NMC does not change what attention computes. It changes where selected reduction happens.

The Technology

SoftChip’s core technology is DRDCL — Dynamically Reconfigurable Differential Cascode Logic.
DRDCL builds on foundational differential cascode logic developed at IBM and extends it with dynamic Cross-Switch reconfiguration.
The result is a logic structure that can share evaluation across related functions and, in some configurations, generate multiple useful outputs from the same input evaluation.

  • multiple functions per evaluation
  • multiple useful outputs
  • dynamic Cross-Switch output selection
  • lower intermediate switching
  • fewer local reduction/control stages
  • improved useful work per watt and area

This foundation enables new classes of macro IP for AI, memory-interface logic, control/dataflow, arithmetic, and adaptive compute.

Working With Us

SoftChip works with semiconductor, AI hardware, and foundry ecosystem partners to evaluate DRDCL logic IP against equivalent conventional CMOS implementations.

Initial engagements focus on bounded, characterizable logic blocks with clear PPA targets, integration assumptions, and benchmark criteria.

  • proof-of-concept logic development
  • NRE-funded evaluation
  • foundry-compatible characterization
  • customer-specific implementation
  • IP licensing

Soft-NMC, Soft-TTC, and future DRDCL-enabled architectures build on this characterizable-logic foundation.