DRDCL: A New Digital Logic Structure
More useful computation per transistor, per cycle, per mm² and per watt.
SoftChip has developed DRDCL, a proprietary digital logic structure built on an inherently more efficient CMOS architecture.
The innovation enables nanosecond-scale reconfiguration among different required functions and multiple simultaneous useful outputs from a single evaluation. The result is higher effective throughput, lower power and energy, and greater area efficiency.
Soft-NMC is the first commercial application, using DRDCL near the memory boundary to reduce K/V- derived movement during AI inference.
Rethinking How Logic Is Built
Traditional digital logic often requires repeated structures and multiple stages to perform related functions.
DRDCL takes a different approach. It uses an inherently more efficient CMOS logic structure to perform more useful computation from each evaluation.
It reduces transistor count, intermediate switching, routing complexity, latency, power dissipation, and data movement while supporting multiple functions over time and multiple simultaneous useful outputs from a single evaluation.
More useful work per evaluation.
Making Every Transistor Do More
- multiple simultaneous outputs
- 2×+ faster
- less switching activity
- lower power and energy
- higher effective throughput
- greater area efficiency
“We’re not trying to make transistors smaller. We’re making them do more.”
More Useful Computation from Each Evaluated Structure
DRDCL can perform related functions through a common evaluation rather than building a separate fixed network for every function and output. This can increase effective throughput, reduce intermediate stages and switching, and improve useful computation per watt and per unit of area.
- higher effective throughput
- fewer intermediate steps
- reduced switching activity
- lower dynamic power
- smaller area for equivalent work
In DRDCL, density is not the starting assumption.
It is the result of doing more useful computation inside fewer structures.
Characterizable Logic Blocks First
SoftChip delivers DRDCL as bounded logic blocks built in standard CMOS and designed for straightforward integration into existing semiconductor architectures.
Each block is characterized for timing, power, area, and PVT, with conventional interfaces and design views for use in established EDA flows.
Reducing Data Movement in AI Inference
AI inference is increasingly constrained by inefficient data movement across the memory hierarchy.
SoftChip’s first commercial application, Soft-NMC, applies Stream / Reduce / Accumulate logic near the memory boundary to perform scoring, selection, reduction, accumulation, gating, and local state updates before unnecessary intermediate data travels deeper into the accelerator.
The goal is to reduce K/V-derived movement, improve sustained tokens per second, and lower power and area for memory-bound inference.
Architecture-Model Targets
- 60–80% less K/V-derived movement
- 12–13× higher local throughput
- 3–4× potential sustained system throughput in memory-bound inference
- under 1% targeted area overhead at the memory-channel boundary
Model Qualification
These are mathematical architecture projections, not measured silicon results.
Soft-NMC does not change what attention computes. It changes where selected reduction happens.
Built on Proven Differential Logic
DRDCL builds on Differential Cascode Voltage Switch logic, developed at IBM for high-speed, low-power digital design.
SoftChip extends that foundation with dynamic Cross-Switch reconfiguration, multiple simultaneous outputs, and emerging in-logic state retention.
Working With Us
SoftChip works with semiconductor, AI hardware, and foundry ecosystem partners to evaluate DRDCL logic IP against equivalent conventional CMOS implementations.
Soft-NMC and future DRDCL applications build on this bounded, characterizable logic-block foundation.